1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically relates to the connection portion where a macro circuit is connected to an outer extension wiring.
2. Description of the Related Art
A conventional technique of the extension wiring connected to a macro circuit will be described below by exemplifying a test pattern for a process evaluation in a typical semiconductor device. FIG. 1 shows a plan view of an example of the layout of a test chip for a process evaluation. Typically, the maximum value of a lateral width 801 and a longitudinal width 802 of a test chip size is defined in the field size of a lithography apparatus. The evaluation pattern consists of a set of evaluation blocks referred to as sub chips 803, and the sizes of the sub chips 803 are equally configured inside test blocks (refer to “Advanced Process Technology 2003, Backend Process: Section 5. 200 nm pitch double layer Cu interconnection TEG and module results”, URL: “http://www.selete.co.jp/SeleteHPJ1/j_html/research/re0022.html”, search date is Feb. 1, 2005). The reason is that since the arrangements and movements of measuring probes is set to be equal in a measuring program, the programs and the measuring probes can be shared. Next, the schema of the pattern for an interconnection process evaluation is explained with reference to FIG. 2. The pattern for the interconnection process evaluation includes a via chain, an electro migration evaluation pattern, a leak measurement pattern and the like. In the via chain, the pattern scale is generally changed on the basis of the length of the interconnection to be evaluated and the number of the via holes. By changing the pattern scale, it is also possible to evaluate the defect density. The evaluation block required to evaluate the process is referred to as a TEG (Test Element Group) region 901, an electrode with which an electrically measuring probe is brought into contact is referred to as an electrode pad 902, and an interconnection through which the TEG region 901 and the electrode pad 902 are connected is referred to as an extension wiring 903.
FIG. 3 shows an enlarged view of an example of the connection region between the TEG region and the electrode pad. As shown in FIG. 3, a via chain pattern 1001 in the TEG region and the electrode pad (not shown) are electrically connected through an extension wiring 1002.
FIG. 4 shows an enlarged plan view of the connection portion to the via chain portion of the extension wiring shown in FIG. 3. As shown in FIG. 4, the width of the interconnection 1102 connected to a via chain portion 1101 is same to the width of the via chain portion 1101 from a region entering the via chain.
FIG. 5 shows an enlarged plan view of the interconnection to a specified pad interconnection. For example, as shown in FIG. 5, the test pattern is provided with a via chain evaluation TEG region 1201 and an extension wiring 1202 for establishing the electric connection to a pad (not shown). The TEG region 1201 has a two-layer interconnection structure where M1 interconnections (belonging to first layer interconnections) 1204 and M2 interconnections (belonging to second layer interconnections) 1203 are alternately arranged. The M1 interconnection and the M2 interconnection are connected through a via 1205. Here, both widths of the M1 interconnection 1204 and the M2 interconnection 1203 are 70 nm that is a minimum interconnection width 1206. In an isolated interconnection portion (an extension wiring 1202) extended from the TEG region 1201 to outside, the interconnection width is stepwise large, and an interconnection width 1207 of the wide portion is about 0.17 μm. A connecting distance 1208 between the wide interconnection portion and the TEG region 1201 is represented in FIG. 5.
FIG. 6 shows a sectional view of the test pattern shown in FIG. 5. As shown in FIG. 6, an insulating film 1304 is formed over a silicon substrate 1303, the M1 interconnections 1204 and the M2 interconnections 1203 are alternately arranged in this region, and those interconnections are connected through the via 1205. Here, both widths of the M1 interconnection 1204 and the M2 interconnection 1203 are 70 nm that is the minimum interconnection width. A margin at the end portions of the M1 interconnection 1204 and the via interconnection 1205 is referred to as an extension 1308.
Next, a process for forming the typical two-layer interconnection is explained. FIGS. 7A to 7E are sectional views of major steps.
At first, a CVD method and the like are applied to form an first interlayer insulating film 1402, which is made of silicon oxide film and the like, on a silicon film 1401 (FIG. 7A). After that, a first photolithography resist 1403 is formed on the first interlayer insulating film 1402, and the resist is patterned by applying a first photolithography method (FIG. 7B). Moreover, after this resist pattern is printed on the first interlayer insulating film 1402 by applying a dry etching technique, the resist 1403 is removed, thereby forming an interconnection trench 1404 at appropriate positions (FIG. 7C).
Next, the CVD method and the like are applied to form a conductive film 1405 made of copper, aluminum and the like on the whole surface of the first interlayer insulating film 1402 including the interconnection trench 1404 (FIG. 7D). Or the barrier metal layer is formed through sputtering method and copper plating is applied so that the level difference on the surface is covered and flattened. Then, CMP is applied for etching back to flatten the surface of the conductive film 1405. As a result, a first interconnection 1406 of a damascene interconnection structure is formed at a desirable position of the first interlayer insulating film 1402 (FIG. 7E).
After forming the M1 layer interconnections by the process described above, the process including the steps similar to the steps shown in FIGS. 7A to 7E is applied to the upper surface of the M1 layer including the forming of a via mask and a M2 mask so that the double-layer interconnection device is manufactured.
The conventional technique in a typical CPU logic circuit will be described below. The structure of an interconnection to an electrically integrated circuit block from an isolate circuit block is described by exemplifying this conventional example, because the similar structure is used not only in the TEG extension wiring for the process evaluation but also in products.
The product is provided with four macro functions of an I/O block, a RAM unit, a logic unit and PLL. The schematic structure is shown in FIG. 8.
In FIG. 8, an I/O block 1501 is an area in which the widths of the interconnections are 1 μm or more. Basically, there is no need of narrower interconnection in this area. The allowable capacity limit on a large current is determined by this area, and the maximum values of the interconnection width and the via diameter are determined by this area. As for an I/O input, typically, there are one output and one input interconnection for a pad block.
The typical memory size of the RAM block 1502 is about 1 megabyte. In this area, priority is given to the fineness of the structure over the high-speed of the interconnections so that the need of the narrow interconnections is high. The wide interconnection is relatively little, and power sources and GND interconnections are periodically aligned at a unit of a memory cell size.
A high performance logic block 1503 is a cell that requires a drive performance, and block where a power source interconnection is enhanced. Basically, the structure of this block is close to the standard cell configuration of the gate array. Although the configuration of the interconnection is similar to that of the RAM, the power source interconnection is typically enhanced over the RAM. As compared with the PLL, typically, there are a plurality of connections connecting between the macro circuits.
In a PLL block 1504, priority is given to the stability of the operation of the power source, GND and capacitive elements. Thus, although the interconnection density is smaller, typically, the interconnection width is wide next to the I/O region. The PLL amplifies a signal input from an external transmitter by 4 times or 5 times or the like and generates a clock tree for each macro. This clock input unit and clock output unit serve as the extension wiring from the macro circuit. Basically, there are only two input/output interconnections.
In this typical interconnection arrangement structure, the block connection structure of two logic unit macro circuits are explained with reference to FIG. 9.
In FIG. 9, a logic region (macro circuit region) 1601, a second logic region (macro circuit region) 1602, and an intermediate region 1603 between the macro circuits are shown. A power source mesh 1604 and a GND mesh 1605 are arranged in the macro. A wire interconnection and a signal interconnection 1606, which serve as circuit configuration elements, are arranged between the power source mesh 1604 and the GND mesh 1605 in the macro. Moreover, signal interconnections for connecting the macros are shown. A connection region 1607 between those signal interconnections are drawn in FIG. 9. There is a case that the interconnections between the macros are connected through the same interconnection layer, or there is a case that they are connected through different interconnection layers.
As mentioned above, in the conventional CPU logic circuit, the interconnection having minimum width or constant width is extended from a macro circuit to outside and connected to the circuit outside the macro.